Keynote 2019: RISC-V and the Future of Computing

Ted Speers, Head of Product Architecture and Planning, Technical Fellow at Microchip Technology Inc., has promised a ‘thought provoking, historical and interesting’ opening keynote at FPGA-forum 2019.

A useful way to look at a computer system is to view it an organism comprised of nerve endings (devices, sensors and actuators), nerves (gateways and transport) and the brain (data centers and the cloud). We’ve gone through at least three major stages of evolution of this organism, starting with telephony and moving to computing and then mobile.  In this talk, we’ll review how this system has evolved, how value was captured at each stage of evolution and project how this system is poised to evolve in the post Moore’s Law era and the role that the RISC-V ISA will play in that evolution.

Maybe we will also hear something about the acquisition of Microsemi?


Ted Speers is head of product architecture and planning for the programable solutions business unit at Microsemi, a wholly owned subsidiary of Microchip Technology, where he is responsible for defining the roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Microsemi in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. Ted is a Technical Fellow and co-inventor on 35 U.S. patents. Prior to joining Microsemi, he worked at LSI Logic. He has a Bachelor of Science in chemical engineering from Cornell University. Ted has been a member of the RISC-V Foundation Board of Directors since its inception in 2016.